In the second blog post of this feature, we showed you how to capture interrupt signals. This post is our third and final of our series on how to easily debug embedded interrupts. In this post, we will take you through how to use Logic’s measurement capability.
With our signals captured, we can determine intervals of interest using Logic’s measurement capability. Measurements can be made from a saved capture as well; to load a saved capture, on the right-hand side of Logic’s display, Options->Open Capture. Logic opens the capture at the same viewing location from when it was saved. Moving the mouse pointer to an event of interest displays the associated timing. Double-click on a signal transition to horizontally zoom in. Position the mouse pointer at the left edge of a channel display, and a left-pointing arrow appears; click on it to advance to the previous edge in that direction. On the keyboard, CTRLPLUS also zooms in, and CTRLMINUS zooms out.
Logic allows us to to measure timing in our ISR by moving Timing Markers to relative locations in the capture, and Logic computes and displays the result for us. On the right-hand side of Logic’s display, look for the Timing Marker Pair A1 and A2. Using the mouse, click and drag A1 and A2 to points on the capture and Logic will display the time difference A1 – A2. We can use this to measure the performance of our ISR.
Drag A1 to the falling edge of INT0, and drag A2 to the falling edge of Output1 (ISR Active); from this measurement the minimum time required from the assertion of the external interrupt INT0 to the ISR entry is 1.75 microseconds. The minimum time to enter the ISR may be critical; if a device needs service faster than this minimum, a designer may have to increase clock speed.
Drag A1 to the falling edge of Output1 (ISR Active) and drag A2 to the rising edge of the same signal; from this measurement the running time required for the simulated work done in the ISR is 17.33 microseconds. The running time of ISRs should usually be kept as short as possible, and Logic helps us measure the time required so we can evaluate the performance impact of changes to our code.
Drag A1 to the falling edge of INT0, and drag A2 to the rising edge of Output2 (ISR Done); from this measurement the minimum time required from the assertion of the external interrupt INT0 until the ISR completes and control is returned to main is 20 microseconds. The minimum time to fully service an interrupt and return control to main with interrupts enabled and ready to service a subsequent interrupt may be a limiting factor in a system’s capabilities. If servicing interrupts can’t be done fast enough, a designer may need to re-engineer the system to accomodate the service rates available, or take other actions to increase the interrupt service rate.
This video shows our measurement scenario, working with a saved capture:
We have shown how to use Logic 4 to debug embedded interrupt issues in a typical embedded system. Logic 4 provides the visibility to understand and verify the timing and correctness of embedded code.